| Popis: |
This study aims at comparing two subthreshold flip-flop architectures in frequency divider applications, implemented and fabricated in 130 nm CMOS process technology. They are the Power PC (Performance Computing) and Nand race-free flip-flops. Identification of a reliable and power efficient flip-flop, used in a frequency divider for ultra-low supply voltages, has been verified by measurements. The simulated results based on a netlist extracted from layout show that upsizing the Power PC flip-flop increases it's reliability while it may still provide lower power consumption than the Nand race-free flip-flop. Based on results verified by measurements for ten chip samples, both frequency dividers have demonstrated functionality down to a V dd of 135 mV. The Power PC flip-flop based frequency divider is 24% more energy efficient than the Nand race-free counterpart at an ultra-low supply voltage of 160 mV. The energy per operation for the Power PC- and Nand race-free- frequency dividers at the minimum energy point (MEP) of 250 mV, and maximum operating frequency, are 12.2 and 12.5 fJ, respectively. |
