A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS
| Autor: | Brent Carlton, Kailash Chandrashekar, Somnath Kundu, Likai Chai, Stefano Pellerano |
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| Rok vydání: | 2021 |
| Předmět: |
Bit time
Comparator Computer science 020208 electrical & electronic engineering dBc 02 engineering and technology Ring oscillator Phase-locked loop CMOS Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Figure of merit Time domain Digitally controlled oscillator Electrical and Electronic Engineering Jitter |
| Zdroj: | IEEE Journal of Solid-State Circuits. 56:43-54 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | This article describes a synthesized fractional- $N$ multiplying delay-locked loop (MDLL) implemented in Intel 22-nm FFL FinFET technology. A 2-bit time-period comparator (TPC) is proposed to adjust the ring oscillator frequency to suppress the spurs without introducing errors due to its inherent phase offset. A programmable delay is used to compare the periods of the MDLL output in time domain, reducing power consumption and making the design synthesizable. TPC 2-bit output achieves fast and robust locking without any initial calibration. The fractional multiplication ratio is achieved by using a digital-to-time converter (DTC) in the reference path with a replica of the digitally controlled oscillator (DCO) to automatically achieve a range of one DCO period. Any variation in DTC delay due to gain mismatch is corrected by a digital loop operating in the background. A detailed analysis of the small-signal model and noise of the proposed MDLL has also been presented. The core area of the synthesized design is 0.0052 mm2 while operating over the frequency range from 1.2 to 3.8 GHz. The integrated rms jitter is 2.74 ps, and the spurs are below −47 dBc measured at 3.6175 GHz. Fractional- $N$ MDLL power consumption is 3.19 mW with the figure of merit (FOM) of −226.3 dB. |
| Databáze: | OpenAIRE |
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