Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS
| Autor: | Ming-Ta Yang, T. Chalvatzis, Sorin P. Voinigescu, K.H.K. Yau, R.A. Aroca, Peter Schvan |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Transimpedance amplifier
Engineering business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY law.invention CMOS Hardware_GENERAL law Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering Operational amplifier Inverter Current-mode logic Electrical and Electronic Engineering business Retiming Flip-flop Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 42:1564-1573 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.2007.899093 |
| Popis: | This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-VT MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design. |
| Databáze: | OpenAIRE |
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