An ultra low-power DAC with fixed output common mode voltage
| Autor: | Roghayeh Saeidi, Mohammad Sharifkhani, Ata Khorami |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Comparator
Computer science 020208 electrical & electronic engineering Linearity 020206 networking & telecommunications Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Converters law.invention Capacitor CMOS law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Common-mode signal Electrical and Electronic Engineering Voltage |
| Zdroj: | AEU - International Journal of Electronics and Communications. 96:279-293 |
| ISSN: | 1434-8411 |
| DOI: | 10.1016/j.aeue.2018.09.031 |
| Popis: | A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. |
| Databáze: | OpenAIRE |
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