A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Autor:	H. Matsuoka, Atsushi Hachisuka, Hideyuki Noda, K. Shigeta, Kenji Anami, Fukashi Morishita, Isamu Hayashi, A. Amo, M. Niiro, M. Okamoto, T. Gyohten, Tatsuo Kasaoka, Katsumi Dosaka, K. Takahashi, Kazutami Arimoto, H. Shinkawata, T. Yoshihara, K. Fujishima
Rok vydání:	2005
Předmět:	Dynamic random-access memory Engineering business.industry Integrated circuit RC time constant Chip law.invention CMOS law Low-power electronics Electronic engineering System on a chip Electrical and Electronic Engineering business Computer hardware Dram
Zdroj:	IEEE Journal of Solid-State Circuits. 40:204-212
ISSN:	0018-9200
DOI:	10.1109/jssc.2004.837986
Popis:	An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::31bb5c834b4cc5e50f645e3bcab987de https://doi.org/10.1109/jssc.2004.837986 Zobrazit plný text záznamu