Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor
| Autor: | Irina Kataeva, Henrik Engseth, Anna Kidiyarova-Shevchenko |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Multiplication algorithm
Digital signal processor Hardware_MEMORYSTRUCTURES business.industry Computer science CPU cache Clock rate Condensed Matter Physics Electronic Optical and Magnetic Materials CMOS Rapid single flux quantum Multiplication Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Accumulator (computing) business Computer hardware |
| Zdroj: | IEEE Transactions on Applied Superconductivity. 17:486-489 |
| ISSN: | 1051-8223 |
| DOI: | 10.1109/tasc.2007.901451 |
| Popis: | We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2 process. |
| Databáze: | OpenAIRE |
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