A VLSI Design approach for RISC based MIPS architecture

Autor:	Munmun Ghosal, A. Y. Deshmukh
Rok vydání:	2012
Předmět:	Very-large-scale integration business.industry Computer science Pipeline (computing) Control unit Instruction set Embedded system Execution unit Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING Architecture business Interlock Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ModelSim
Zdroj:	Proceedings of the First International Conference on Pervasive Computing and Communication.
DOI:	10.3850/978-981-07-2579-2_pcc-243
Popis:	This paper describes the design and analysis of the functional units of RISC based MIPS architecture. The functional units includes the Instruction fetch unit, instruction decode unit, execution unit, data memory and control unit. The functions of these modules are implemented by pipeline without any interlocks and are simulated successfully on Modelsim 6.3f and Xilinx 9.2i. It also attempts to achieve high performance with the use of a simplified instruction set. KeywordsMIPS, RISC, Pipelining, Memory.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::31851d2fa3a8c83ae4a86a55de6b5db8 https://doi.org/10.3850/978-981-07-2579-2_pcc-243 Zobrazit plný text záznamu