Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling
| Autor: | Marios C. Papaefthymiou, Taewhan Kim, Minseok Kang, Seyong Ahn |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
Synchronous circuit business.industry Clock signal Underclocking 020208 electrical & electronic engineering Clock rate Clock gating 02 engineering and technology Digital clock manager Clock skew Computer Graphics and Computer-Aided Design 020202 computer hardware & architecture 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering business Software CPU multiplier |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:2068-2081 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2016.2543022 |
| Popis: | The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissipate. On the other side, it has been known that dynamic voltage-frequency scaling (DVFS) is one of the most effectively and widely used power reduction techniques. However, so far no works have addressed the design methodology problem of synthesizing resonant clock networks that are able to operate under the designs with DVFS capability even though the problem is potentially very important to maximize the synergy effect on saving power. In this context, this paper proposes a comprehensive solution to the problem. Precisely, we propose a two-phase synthesis algorithm: 1) formulating the problem of inductor allocation, placement, and adjustable-sizing to support DVFS into a weighted set cover problem with the objective of minimizing total area of inductors and 2) followed by performing the task of resizing of adjustable driving buffers to support the switch of driving strength according to the clock frequencies by DVFS. Through experiments with benchmark circuits, it is shown that for designs with DVFS using 1 and 3 GHz, our algorithm synthesizes resonant clock networks with 25.9% less power on the execution of the clock frequency, which is not supported by resonant clocking in the previous no-DVFS aware resonant clock synthesis algorithm. |
| Databáze: | OpenAIRE |
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