HUB Floating Point for Improving FPGA Implementations of DSP Applications
| Autor: | Julio Villalba, Javier Hormigo |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Adder
Forcing (recursion theory) Floating point Computer science business.industry Rounding 020208 electrical & electronic engineering 02 engineering and technology 020202 computer hardware & architecture Computer Science::Hardware Architecture 0202 electrical engineering electronic engineering information engineering Fpga implementations Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Field-programmable gate array Implementation Digital signal processing Computer hardware |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 64:319-323 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2016.2563798 |
| Popis: | The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on DSP application implementations. We then present a detailed study of the improvement achieved when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the cases studied, the HUB approach reduces resource use and increases the speed of these FP units while always providing statistically equivalent accuracy as that of conventional formats. However, for some specific sizes, HUB multipliers require far more resources than the corresponding conventional approach. |
| Databáze: | OpenAIRE |
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