An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation
| Autor: | Qingji Sun, Shigetoshi Nakatake, Chao Geng |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Artificial neural network Computer science 020208 electrical & electronic engineering Process (computing) 020206 networking & telecommunications Error ratio Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology ComputerSystemsOrganization_PROCESSORARCHITECTURES Dissipation Perceptron CMOS Multilayer perceptron Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_LOGICDESIGN Voltage |
| Zdroj: | MOCAST |
| DOI: | 10.1109/mocast49295.2020.9200299 |
| Popis: | This paper presents an analog circuit comprising a multi-layer perceptron (MLP) applicable to the neural network(NN)-based machine learning. The MLP circuit with rectified linear unit (ReLU) activation consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Our MLP circuit is implemented in a 0.6 μ m CMOS technology process with a supply voltage of ± 2.5 V. An experimental case is conducted to demonstrate the feasibility and effectiveness of the MLP circuit. The simulation results show that our MLP circuit has a power dissipation of 200mW, a wide range of working frequency from 0 to 1MHz, and a moderate performance in terms of the error ratio. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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