Vdd/2 clock swing D flip-flop using output feedback and MTCMOS
| Autor: | S.h. Lin, Huazhong Yang |
|---|---|
| Rok vydání: | 2006 |
| Předmět: |
Output feedback
Hardware_MEMORYSTRUCTURES Bistability Computer science Active mode Hardware_PERFORMANCEANDRELIABILITY Swing Dissipation law.invention law Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering Standby power Flip-flop Hardware_LOGICDESIGN Leakage (electronics) |
| Zdroj: | Electronics Letters. 42:853 |
| ISSN: | 0013-5194 |
| Popis: | By using output feedback and MTCMOS, a low clock swing D flip-flop is proposed. Experimental results show that the leakage and total power of the proposed flip-flop can be reduced by an average of 58.14 and 55.76% in standby mode and in active mode, respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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