A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS
| Autor: | Tetsuya Iida, H. Ishii, Ken Tanabe |
|---|---|
| Rok vydání: | 2005 |
| Předmět: |
Engineering
business.industry Pipeline (computing) Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Decoupling capacitor law.invention Capacitor CMOS Hardware_GENERAL Power consumption law Hardware_INTEGRATEDCIRCUITS Electronic engineering Operational amplifier Hardware_ARITHMETICANDLOGICSTRUCTURES business Voltage reference Voltage |
| Zdroj: | CICC |
| DOI: | 10.1109/cicc.2005.1568688 |
| Popis: | A 1.0V 10b 100MS/s pipeline ADC consuming 40mW fabricated in a 90nm CMOS process is described. Design consideration for the thermal noise of operational amplifiers effectively saves the power consumption of the ADC with conventional architecture at 1.0 V supply. Measured peak SNDR of the ADC is 56.5dB. It occupies 0.52 mm2 with on-chip decoupling capacitors and 0.31 mm2 without the capacitors, both of which includes the buffer for reference voltages |
| Databáze: | OpenAIRE |
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