Autor: |
M.F. Beug, Mark Isler, T. Melde, Christoph Ludwig, Klaus Knobloch, L. Bach, S. Riedel, M. Ackermann |
Rok vydání: |
2008 |
Předmět: |
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Zdroj: |
2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design. |
DOI: |
10.1109/nvsmw.2008.42 |
Popis: |
This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the areas above source and drain. This effect significantly deteriorates the erase performance of charge trapping devices compared to the intrinsic erase behavior which can be measured at large area capacitor structures. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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