A Seven-Level VSI With a Front-End Cascaded Three-Level Inverter and Flying-Capacitor-Fed H-Bridge
| Autor: | Kirubakaran Annamalai, Tirupathi Abhilash, Somasekhar Veeramraju Tirumala |
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| Rok vydání: | 2019 |
| Předmět: |
Computer science
business.industry Electrical engineering Topology (electrical circuits) H bridge Network topology Industrial and Manufacturing Engineering law.invention Capacitor Control and Systems Engineering law Logic gate Inverter Electrical and Electronic Engineering business Reduced cost Voltage |
| Zdroj: | IEEE Transactions on Industry Applications. 55:6073-6088 |
| ISSN: | 1939-9367 0093-9994 |
| DOI: | 10.1109/tia.2019.2933378 |
| Popis: | Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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