Drain-induced barrier lowering in buried-channel MOSFET's
| Autor: | M.J. Van der Tol, S.G. Chamberlain |
|---|---|
| Rok vydání: | 1993 |
| Předmět: |
Materials science
Channel length modulation Computer simulation Subthreshold conduction Reverse short-channel effect business.industry Drain-induced barrier lowering Electronic Optical and Magnetic Materials Threshold voltage MOSFET Electronic engineering Optoelectronics Field-effect transistor Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Electron Devices. 40:741-749 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/16.202786 |
| Popis: | In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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