| Autor: |
Rajendra Chikkanagouda, P. Cyril Prasanna Raj |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
2019 International Conference on Communication and Signal Processing (ICCSP). |
| Popis: |
This paper presents a Low Noise Amplifier (LNA) modeled in 65 nm CMOS technology for wideband (110-135) GHz systems. LNA comprises of four stages cascode with L-type matching networks used for input and interstage matching and T-Shape matching networks used at output side. The first stage is designed to improve the noise and input matching and subsequent stages for gain performance. The LNA achieves a flat gain response over a wide bandwidth. The amplifier design is modeled and simulated in Advanced Design System (ADS). The LNA achieves a high gain of 29.11 dB at 124 GHz, Noise Figure (NF) less than 5.2 dB and 3 dB bandwidth of 20 GHz. The S 11 is -19.91 dB at 128 GHz. The LNA dissipates power of 20 mW with 1.8 V supply voltage. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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