Analysis, Design, and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs
| Autor: | Sung Joo Park, Nitish Natu, Madhavan Swaminathan |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Engineering
Clock signal business.industry Electrical engineering Skew Power integrity Clock gating Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Signal Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials law.invention law Gate array Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering Power network design business |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 5:1669-1678 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2015.2482947 |
| Popis: | The 3-D integrated circuits (3-D ICs) overcome the bottlenecks in system performance and circuit density. However, their increased power and thermal density cause temperature gradients in the chip that significantly affect signal and power integrity. Temperature gradients significantly degrade the clock signal, a key signal in digital systems, which in turn degrades system performance. In this paper, we investigate the effect of thermal gradients on the clock distribution network in the 3-D ICs along with the power distribution network. We also present power-efficient compensation methods for minimizing temperature-induced skew using the thermoelectrical analysis and use them to design a custom IC in which we compare the skew, the power, and the area. Finally, using measurements, we validate the design with a field-programmable gate array-based test vehicle. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|