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Spin-orbit torque magnetic random access memory (SOT-MRAM) is considered as one of the most promising technologies to replace or co-exist with the current leaky CMOS charge based memories such as SRAM and DRAM, thanks to SOT-MRAM's non-volatility, high energy efficiency, endurance and reliability. However, conventional SOT-MRAM bit-cell [1] requires two access transistors to fully separate the selected bit from the non-selected bits, which limits the density of SOT-MRAM. Hence, in this work, we propose a diode based multilevel cell (MLC) SOT-MRAM with only one access transistor per 2-bits, which will at least double the density compared to various designs in the literature. Our proposed cell, shown in Fig. 1(a), employs a shared diode between two in-parallel MTJs to eliminate the need for a read transistor. The diode is oxide based, thus, it can be 3D stacked over the MTJs and does not consume any additional silicon area. The employed diode is unidirectional, where it conducts current only under forward bias. In SOT programming, the read transistor only needs to supply a relatively small unidirectional read current (10's of $\mu \mathrm {A})$ during the read operation. Hence, the proposed shared diode can satisfy the requirements to replace the read transistor in conventional SOT-MRAM. The two MTJs are connected in-parallel and have different low $( \mathrm {R}_{P})$ and high $( \mathrm {R}_{AP})$ electrical resistances. Four different states could thus result based on their equivalent resistance. The four resistance states can thus be mapped into four different 2-bit configurations, i.e., '00', '01', '10' and '11'. The two MTJs are placed in-contact to a common heavy metal (HM) electrode that allows accessing the two MTJs (i.e., 2 bits) using only single transistor. The bias conditions for the different signals during read/write operations in our proposed cell are shown in Fig. 1(b). During the write operation, all the RWL signals are pulled low to ensure that the diodes in all cells are reverse biased and no leakage current would flow across the cells. In addition, the WWL of the row comprising the targeted cell is set high to activate the cell's write access transistor. To write a '0' ('1') on either of the MTJs, the BL and SL of the column comprising the targeted cell are asserted high (low) and low (high), respectively. This permits the write current $( \mathrm {I}_{write})$ to flow through the HM electrode in the essential direction, as indicated in Fig. 1(a). It should be pointed out that to permit writing the two MTJs per cell with different data, the two SOT-MTJs are designed to have different critical currents I c . Hence, they require different switching time for the same supplied $\mathrm {I}_{write}$. Writing the two MTJs with identical data ('00'or '11') is done simultaneously by passing $\mathrm {I}_{write}$ with one longer pulse width that follows the SOT-MTJ with longer switching time requirement, under spin charge conservation assumption. To program the $2 ^{nd}$ bit differently, i.e., '01'or'10', $\mathrm {I}_{write}$ with shorter pulse width is sent subsequently. Due to the larger I c of $1 ^{st}$ bit, the $2 ^{nd}$ write pulse would not vary the bit-content of $1 ^{st}$ bit. SOT-MTJs with distinct I c can be realized by either employing MTJs with different free layer thicknesses $( \mathrm {t}_{fl})$ or using different widths of the HM $( \mathrm {W}_{HM})$ below each MTJ, as both $\mathrm {t}_{fl}$ and $\mathrm {W}_{HM}$ have a direct impact on the SOT-MTJ'$mathrm{sI}_{c}$. During the read operation, the WWL signals are pulled low to deactivate all the write transistors, allowing the read current to flow through the targeted MTJs by activating its corresponding RWL. Thereafter, the SL of the column comprising the targeted cell is set to ground, while its row RWL is connected to the sense amplifier to forward-bias the diode. Depending on combined resistance states of the two MTJs, four different currents level could be sensed by the amplifier, which can then be mapped into the corresponding 2-bit stored data. The proposed cell operation is validated in $\mathrm {a}2 \times 2$ array as shown in Fig. 1(c). The simulations are performed using a Verilog-A model of a SOT-MTJ and a diode with a 32-nm CMOS technology library. As demonstrated in Table I, our proposed cell offers at least 50% smaller 1-bit effective area compared to other designs with nearly similar energy consumption. Furthermore, the in-parallel combination of the two MTJs results in lower overall equivalent resistance, which permits reducing the read voltage compared to design in [2] that uses a diode with single MTJ stack. In addition, an improvement of at least 30% in a figure-of-merit defined as energy area product is obtained compared to various designs. |
