Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology

Autor:	J. Burnette, Naveen Javarappa, Brian J. Campbell, V. von Kaenel
Rok vydání:	2007
Předmět:	business.industry Computer science Latency (audio) Clock gating Floorplan Tag RAM CMOS Hardware_INTEGRATEDCIRCUITS Electronic engineering Bandwidth (computing) System on a chip Cache business Computer hardware
Zdroj:	CICC
DOI:	10.1109/cicc.2007.4405834
Popis:	The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::2e8a82d7102400ee7fe6fdb175e12517 https://doi.org/10.1109/cicc.2007.4405834 Zobrazit plný text záznamu