Design of Low Power Sequential Circuit by using Adiabatic Techniques
| Autor: | Priyanka Ojha, Charu Rana |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Adiabatic circuit
Control and Optimization Sequential logic Pass transistor logic Computer Networks and Communications Computer science Logic family Hardware_PERFORMANCEANDRELIABILITY Circuit extraction Computer Science Applications Human-Computer Interaction Computer architecture Artificial Intelligence Modeling and Simulation Signal Processing Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_LOGICDESIGN Register-transfer level Asynchronous circuit Logic optimization |
| Zdroj: | International Journal of Intelligent Systems and Applications. 7:45-50 |
| ISSN: | 2074-9058 2074-904X |
| DOI: | 10.5815/ijisa.2015.08.06 |
| Popis: | Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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