A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool
| Autor: | Vinicius Borges, Murilo Perleberg, Marcelo Porto, Vladimir Afonso, Luciano Agostini |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Computer science
1080p 020207 software engineering 02 engineering and technology Dissipation Frame rate Application-specific integrated circuit Gate count VHDL 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Architecture Algorithm computer computer.programming_language Coding (social sciences) |
| Zdroj: | LASCAS |
| DOI: | 10.1109/lascas45839.2020.9068965 |
| Popis: | This paper presents a low-power and high-performance hardware design for the Depth Modeling Mode 1 (DMM-1) of the 3D-High Efficiency Video Coding (3D-HEVC). The designed architecture is based on a low-complexity algorithm developed to reduce the DMM-1 computational effort and to avoid the use of memory. The architecture was described in VHDL, and the ASIC synthesis was performed for the TSMC 40nm technology. The synthesis results showed a gate count of 1,283k gates and a power dissipation of 51.36 mW, when running at 82 MHz. The designed architecture is capable of processing 3D 1080p videos with up to 11 views at 30 frames per second. The reached results surpass the published works in terms of throughput and power dissipation. |
| Databáze: | OpenAIRE |
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