| Popis: |
With scaling of interconnect pitches in advanced process nodes, the ratio of line-edge roughness (LER) to line width increases. At the same time, the application of EUV lithography changes the characteristic LER parameters as compared to traditional lithography. In this paper, we provide an analysis of the impact of LER from wire resistance to system-level performance. Our silicon-calibrated resistance model is extended to include the effect of both LER standard deviation and correlation length, which allows accounting for the impact of wire length on resistance variability. The new resistance model is validated against Raphael simulations after process emulation by Sentaurus Process Explorer, with which realistic roughness can be reproduced by controlling the LER input parameters. A commercial CPU design is used as benchmark to assess system-level impact. After full physical implementation of the design, the impact of LER is modelled in a customized static timing analysis flow. Since LER is a stochastic effect, traditional corner-based modelling is not effective. Instead we propagate the wire resistance probabilities through the timing analysis to obtain a critical-path timing distribution and derive estimates for the impact on yield. Results show that while there is a significant impact of LER on the resistance distribution for short wires, the effect largely averages out on system level with the timing variation within 2 % of the clock period. The impact increases when scaling to narrower wires. In this case, we show that LER impact can be mitigated by using alternative mentalization schemes such as barrierless ruthenium interconnects. |
