An all-digital frequency locked loop and its linearized S-domain model
| Autor: | Robert Groza, Calin Farcas, Marina Topa, Botond Sandor Kirei |
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| Rok vydání: | 2017 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Logic simulation 02 engineering and technology Signal 020202 computer hardware & architecture Loop (topology) Frequency-locked loop Control theory Control system 0202 electrical engineering electronic engineering information engineering Verilog Digital control Digitally controlled oscillator computer computer.programming_language |
| Zdroj: | 2017 International Symposium ELMAR. |
| Popis: | The proposed all-digital frequency locked loop features a digitally controlled oscillator, a counter & latch as a frequency sensor and an accumulator in the control loop. The number of oscillation cycles are counted during a logic high of the reference signal and it is subtracted from a desired value set by the user, thus an error signal is obtained. The error is accumulated, and a digital control word is formed for the digitally controlled oscillator. Discrete time domain equations are devised for the proposed ADFLL, and the convergence to the desired frequency is proven. Moreover, the analysis is completed with the s-domain linearized model of the system. Numerical results comprise simulations carried out in (i) a logic simulator for the Verilog behavioral description of the ADFLL and (ii) a PSPICE simulation for the s-domain model. |
| Databáze: | OpenAIRE |
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