A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

Autor: Michael C. Gill, Oluleye Olorode, Raguram Damodaran, Rama Venkatasubramanian, S. Mullinnix, Dheera Balasubramanian, Naveen Bhoria, Kyle Peavy, Nuruddin Mahmood, Hung Ong, Alan Hales, Krishna Chaithanya Gurram, Shriram D. Moharil, Arjun Rajagopal, David Matthew Thompson, Jonathan (Son) Hung Tran, Jose Luis Flores, Robert Sussman, Timothy D. Anderson, Matthew D. Pierson, Sanjive Agarwala, Soujanya Narnur, Duc Quang Bui, Wu Daniel, Abhijeet Ashok Chachad, Mujibur Rahman, Anthony M. Hill, Dhileep Gopalakrishnan
Rok vydání: 2012
Předmět:
Zdroj: VLSI Design
DOI: 10.1109/vlsid.2012.85
Popis: The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.
Databáze: OpenAIRE