LP-P $$^2$$ IP: A Low-Power Version of P $$^2$$ IP Architecture Using Partial Reconfiguration
| Autor: | Paulo Da Cunha Possa, Naim Harb, Carlos Valderrama, Glauberto Leilson Alves de Albuquerque, Álvaro Avelino, Valentin Obac |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
business.industry
Computer science 020208 electrical & electronic engineering Control reconfiguration Image processing 02 engineering and technology Video processing Energy consumption 020202 computer hardware & architecture Power (physics) Reduction (complexity) Embedded system 0202 electrical engineering electronic engineering information engineering business Field-programmable gate array Efficient energy use |
| Zdroj: | Lecture Notes in Computer Science ISBN: 9783319562575 |
| DOI: | 10.1007/978-3-319-56258-2_2 |
| Popis: | Power consumption reduction is crucial for portable equipments and for those in remote locations, whose battery replacement is impracticable. P\(^2\)IP is an architecture targeting real-time embedded image and video processing, which combines runtime reconfigurable processing, low-latency and high performance. Being a configurable architecture allows the combination of powerful video processing operators (Processing Elements or PEs) to build the target application. However, many applications do not require all PEs available. Remaining idle, these PEs still represent a power consumption problem that Partial Reconfiguration can mitigate. To assess the impact on energy consumption, another P\(^2\)IP implementation based on Partial Reconfiguration was developed and tested with three different image processing applications. Measurements have been made to analyze energy consumption when executing each of three applications. Results show that compared to the original implementation of the architecture use of Partial Reconfiguration leads to power savings of up to 45%. |
| Databáze: | OpenAIRE |
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