| Autor: |
null Hou-Yu Chen, null Chang-Yun Chang, null Chien-Chao Huang, null Tang-Xuan Chung, null Sheng-Da Liu, null Jiunn-Ren Hwang, null Yi-Hsuan Liu, null Yu-Jun Chou, null Hong-Jang Wu, null King-Chang Shu, null Chung-Kan Huang, null Jan-Wen You, null Jaw-Jung Shin, null Chun-Kuang Chen, null Chia-Hui Lin, null Ju-Wang Hsu, null Bao-Chin Perng, null Pang-Yen Tsai, null Chi-Chun Chen, null Jyu-Horng Shieh, null Han-Jan Tao, null Shih-Chang Chen, null Tsai-Sheng Gau, null Fu-Liang Yang |
| Rok vydání: |
2005 |
| Předmět: |
|
| Zdroj: |
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.. |
| Popis: |
For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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