| Popis: |
The System-on-Chip design of specific image analysis architectures, which are based on massively parallel Markov Random Field (MRF) processing principles is so far an unstructured, faultprone and complex task. Up to now neither a systematically derived architecture-template nor an industrial approved tool-chain is available to support the VLSI design task for these kind of digital architectures. In this contribution, we report on a theoretical sound and systematically derived architecture-template for massively parallel MRF processing devices. The paper is finalized by prototypical implementations of selected architecture parts using FPGA technologies. These results demonstrate the capability of the proposed architecture-template and manifest the industrial relevance of the template. |
