| Autor: |
Steven C. Nash, F. Volkringer, Richard French, George J. Collini, Robert H. Fair, Phil Sa, Ben R. Vampatella, Ronald A. DellaGuardia, Chet Wasik, George G. Gifford, V. Nastasi, John Michael Warlaumont, Lars W. Liebmann, David E. Seeger, Denise M. Puisto, Angela C. Lamberti, Thomas Zell, Janet M. Rocque |
| Rok vydání: |
1995 |
| Předmět: |
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| Zdroj: |
SPIE Proceedings. |
| ISSN: |
0277-786X |
| Popis: |
This paper describes results achieved from the fabrication of 64Mb DRAM chips using x-ray lithography for the gate level. Three lots were split at the gate level for exposure with either Micrascan 92 at IBM's Advanced Semiconductor Technology Center (ASTC) or x-ray at the Advanced Lithography Facility (ALF) containing a Helios super-conducting storage ring and a Suss stepper. The x-ray mask was fabricated at MMD (Microlithographic Mask Development Facility) as a two-chip mask containing one chip which had zero defects. To achieve adequate overlay performance between the x-ray exposed gate level and previous optically- printed levels, the mask was fabricated with an intentional magnification correction. The alignment scheme for both Suss and Micrascan was first order to an ASM zero level, and second order to each other. Results from the first lot show 90% of the chips tested achieved a +/- 140 nm target for the Suss to Micrascan overlay. Critical dimension control (across wafer and across chip) was measured and found to be comparable between Suss and Micrascan. Electrical performance was comparable to the optical wafers. Chips were fabricated with zero defects in many of the 1 Mb segments. There were also x-ray fabricated chips which demonstrated 63 Mb addressable bits. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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