| Autor: |
Y.H. Huang, W. C. Chiou, Yi-Chun Shih, T. Y. Wang, W.J. Wu, Y.C. Lin, C.H. Chang, F.W. Tsai, C. H. Tung, S.P. Jeng, Kuo-Nan Yang, Doug C. H. Yu, M. F. Chen, Pang-Yen Tsai, Jing-Cheng Lin, E.B. Liao, Shang-Yun Hou, Hun-Hsien Chang, Y.L. Lin, T.J. Wu, Hung Jeng-Nan, C.L. Yu |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
2010 International Electron Devices Meeting. |
| Popis: |
Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TV's) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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