| Popis: |
Three-dimensional (3D) integration method has become the candidate to extend the Moore's law due to its heterogeneous integration, multiple functionality, and low power consumption. To realize 3D integration, Through-silicon via (TSV) has emerged as a good approach to provide higher wiring density, shorter interconnect, and simpler structure. In this study, the overall processes of TSV including via etching, liner deposition, and copper filling are investigated. First of all, in the etching process, the mechanism and the solution of micro-masking effect were studied. Secondly, in the liner deposition, the analysis of different TSV liners was done by using its step coverage, stress, breakdown voltage, and leakage. Finally, in the process of the copper filling, a novel sealing bump method was proposed because of its advantages in less process steps and the self-formation of bonding pad. Test vehicles, including daisy chain, Kelvin structure, and comb structure, were designed with various sizes of TSV to verify the quality by using electrical measurements. In addition, the design rules of TSV were also investigated with reliability tests on different arrangement and pitch of TSV. This study not only proposes a novel design and structure of sealing bumping TSV method, but also summarizes the integration of this TSV with its excellent electrical property and reliability performance, providing a promising technique for TSV integration in 3D IC. Furthermore, the investigation results of design rules provide a useful guideline of TSV placement in the IC layout for future 3D integration. |
