An SEU resistant 256 K SOI SRAM
| Autor: | Larry R. Hite, H. Lu, D.S. Hurta, W.E. Bailey, Theodore W. Houston |
|---|---|
| Rok vydání: | 1992 |
| Předmět: |
Physics
Nuclear and High Energy Physics business.industry Bipolar junction transistor Electrical engineering Silicon on insulator Nuclear Energy and Engineering CMOS Single event upset Bit error rate Static random-access memory Electrical and Electronic Engineering business Pulse-width modulation Voltage |
| Zdroj: | IEEE Transactions on Nuclear Science. 39:2121-2125 |
| ISSN: | 1558-1578 0018-9499 |
| DOI: | 10.1109/23.211411 |
| Popis: | A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256 K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 degrees C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10% worst-case error rate of 3.4*10/sup -11/ errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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