Efficient implementation of the AES algorithm for security applications
| Autor: | Baher Magdy, Shady Mohamed Soliman, Mohamed A. Abd El Ghany |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Loop unrolling
business.industry Computer science 020208 electrical & electronic engineering 02 engineering and technology Advanced encryption standard algorithm Encryption 020202 computer hardware & architecture Power (physics) Embedded system Dynamic demand 0202 electrical engineering electronic engineering information engineering Algorithm design Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Throughput (business) Algorithm |
| Zdroj: | SoCC |
| DOI: | 10.1109/socc.2016.7905466 |
| Popis: | Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize area, throughput and dynamic power consumption. The first design achieves a throughput of 34.08 Gbps, an operating frequency of 266.29 MHz with 521 slice registers. The second design achieves a throughput of 34.09 Gbps, 674 slice registers and a frequency of 266.33 MHz on a Xilinx 14.2 Virtex-5 XC5VLX50-3 FPGA device. Both designs consumes an approximate value of 455 mW of dynamic power using Vivado 2014.4 on Zynq-7000 XC7Z010clq225-3 FPGA device. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|