Modular architecture for high performance implementation of the FRR algorithm
| Autor: | K. Sapiecha, R. Jarocki |
|---|---|
| Rok vydání: | 1990 |
| Předmět: |
Very-large-scale integration
Signal processing Computer science Pipeline (computing) Fast Fourier transform Fault tolerance Parallel computing Discrete Fourier transform Theoretical Computer Science symbols.namesake Fourier transform Computational Theory and Mathematics Hardware and Architecture symbols Digital signal Algorithm Software |
| Zdroj: | IEEE Transactions on Computers. 39:1464-1468 |
| ISSN: | 0018-9340 |
| DOI: | 10.1109/12.61066 |
| Popis: | A novel VLSI-oriented architecture to compute the discrete Fourier transform is presented. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/t transforms per second, where t is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever is longer. Although the system is not optimal (it achieves O(N/sup 3/ log/sup 4/ N) area*time/sup 2/ performance), the architecture is modular and makes it possible to design a system which performs FFT of any size without any extra circuitry. Moreover, the system can provide a built-in self-test and self-restructuring. The modular system is easy to integrate. Processing elements (PEs) are connected to the neighboring PEs only, and form a linear network easy to implement in two and three dimensions. The number of pins required for a chip does not depend on the number of PEs integrated on it, nor on the size of the transform. The system consists of only one type of integrated circuit with a structure irrespective of the transform size, which considerably reduces the cost of implementation. > |
| Databáze: | OpenAIRE |
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