| Autor: |
Ajay Kallianpur, Ryan Robucci, Sushmita Kadiyala Rao, Chintan Patel, Chaitra Sathyanarayana |
| Rok vydání: |
2012 |
| Předmět: |
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| Zdroj: |
VTS |
| DOI: |
10.1109/vts.2012.6231066 |
| Popis: |
Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to power supply noise. Running full-chip simulations on large designs to predict the noise is time consuming and expensive. Therefore, most existing techniques are based on statistical approaches. In this paper, we propose a current-based dynamic method to estimate power supply noise and use the framework to predict the increase in path delay caused by the variations in power supply voltage without carrying out a full-chip simulation. A convolution-based technique is used to compute the path delays where standalone paths are extracted and simulated. Experimental results reported for estimating noise using the ISCAS-85 benchmark circuit are within 10% of full-chip results. The delay predictions carried out on two other experimental designs using our technique closely match full-chip results with a maximum error of 2%. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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