Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors
| Autor: | Raghavendra K, Joe Augustine, Madhu Mutyam, John Jose |
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| Rok vydání: | 2020 |
| Předmět: |
Router
021110 strategic defence & security studies Multi-core processor Hardware_MEMORYSTRUCTURES Computer science 0211 other engineering and technologies Cache-only memory architecture 02 engineering and technology computer.software_genre 020202 computer hardware & architecture Network on a chip Shared memory 0202 electrical engineering electronic engineering information engineering Operating system Cache Latency (engineering) computer Access time |
| Zdroj: | ICCD |
| Popis: | Multiple cores in a tiled multi-core processor are connected using a network-on-chip mechanism. All these cores share the last-level cache (LLC). For large-sized LLCs, generally, non-uniform cache architecture design is considered, where the LLC is split into multiple slices. Accessing highly shared cache blocks from an LLC slice by several cores simultaneously results in congestion at the LLC, which in turn increases the access latency. To deal with this issue, we propose a congestion management technique in the LLC that equips the NoC router with small storage to keep a copy of heavily shared cache blocks. To identify highly shared cache blocks, we also propose a prediction classifier in the LLC controller. We implement our technique in Sniper, an architectural simulator for multi-core systems, and evaluate its effectiveness by running a set of parallel benchmarks. Our experimental results show that the proposed technique is effective in reducing the LLC access time. |
| Databáze: | OpenAIRE |
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