Design and Implementation of AES Key Generator Based on FPGA

Autor: Guang Hui Cai, Hong Ye Li, Xiao Cong Ma, Hong Chao Sun
Rok vydání: 2014
Předmět:
Zdroj: Advanced Materials Research. 1022:104-107
ISSN: 1662-8985
DOI: 10.4028/www.scientific.net/amr.1022.104
Popis: With the continuous development of computer networks, security of data is particularly important. AES algorithm is the new data encryption standard after DES algorithm, which has a higher security and faster running speed. Since the promulgation, it has been widely analyzed and multi used around the world. AES algorithm is iterative algorithm,which needs a key generator to generate the encryption and decryption keys for each round.The key generator mainly designs two modules including S box replacement (SubWord) module and Cycle left shift (RotWord) module. After processing results and Rcon array XOR, the key generator may generate an expanded key. The whole design has a simple circuit structure, less resource-intensive, fast running speed advantages, with good prospects for practical applications.
Databáze: OpenAIRE