A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
| Autor: | M Birbas, J Kikidis, A. Alexandropoulos, E. Davrazos, Fotis Plessas |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Engineering
General Computer Science business.industry Slew rate law.invention On-die termination Control and Systems Engineering law Robustness (computer science) Electronic engineering Signal integrity Electrical and Electronic Engineering Resistor Stub Series Terminated Logic business Double data rate Voltage |
| Zdroj: | Computers & Electrical Engineering. 38:206-216 |
| ISSN: | 0045-7906 |
| DOI: | 10.1016/j.compeleceng.2011.12.012 |
| Popis: | A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm^2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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