Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons
Autor: | Aruna Kumari Chirapangi, G. M. G. Madhuri, Praveen Kitti Burri, Naga Lakshmi Kalyani Movva |
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Rok vydání: | 2019 |
Předmět: |
010302 applied physics
Comparator Computer science Capacitive sensing Circuit design 020208 electrical & electronic engineering Linearity Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Converters 01 natural sciences Power (physics) CMOS 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS Hardware_ARITHMETICANDLOGICSTRUCTURES Hardware_LOGICDESIGN |
Zdroj: | Advances in Intelligent Systems and Computing ISBN: 9783030166564 ISDA (1) |
Popis: | Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper the power consumption and linearity of SAR ADC are analyzed by using different DAC structures and different SAR Logics. Three types of DAC structures i.e. Capacitive DAC, R-2R resistive DAC, and a CMOS R-2R ladder DAC is employed. Coming to SAR logic, sequential/code register and non-redundant SAR logics are used. Among the all, the CMOS R-2R ladder DAC and non-redundant SAR logic structured SA-ADC is efficient and provides optimum results for all circuit design aspects i.e. power, speed, and area. Along above all designs a dynamic two-stage comparator and the D flip-flops with transmission gates are used due to their energy efficiency and capability of working in low supply voltages. |
Databáze: | OpenAIRE |
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