Automatic Hardware Design Tool Based on Reusing Transformation
| Autor: | Chuan Zhang, Chongzhou Fang, Xiaohu You, Zaichen Zhang |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Computer science
business.industry 020208 electrical & electronic engineering Design tool 0211 other engineering and technologies 02 engineering and technology Reuse Transformation (function) High-level synthesis 0202 electrical engineering electronic engineering information engineering Verilog Design process Field-programmable gate array business computer Computer hardware 021106 design practice & management computer.programming_language Register-transfer level |
| Zdroj: | ASICON |
| DOI: | 10.1109/asicon47005.2019.8983487 |
| Popis: | Automatic hardware design is currently drawing research attentions as it has the potential to free designers from low level manual design process. In this paper, we propose an automatic hardware design tool, which is able to automatically perform reusing transformation on circuits. With the number of available computation modules as input, the proposed hardware design tool automatically designs circuit and generates corresponding register transfer level (RTL) codes in term of Verilog HDL. Our FPGA implementation results show that this design tool can efficiently perform resource planning according to user specifications. |
| Databáze: | OpenAIRE |
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