Fast parallel simulation of a manycore architecture with a flit-level on-chip network model
| Autor: | Shin-haeng Kang, Jintaek Kang, Soonhoi Ha |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
021103 operations research
business.industry Computer science Architectural design 0211 other engineering and technologies 02 engineering and technology 020202 computer hardware & architecture Parallel simulation Design phase Network on a chip Embedded system Scalability 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Architecture business Network model |
| Zdroj: | SAMOS |
| DOI: | 10.1145/3229631.3229647 |
| Popis: | The reliance on simulation for the design of a new architecture continues to increase as the complexity of the architecture increases with more cores integrated and a complex communication fabric. A good compromise between the simulation speed and accuracy should be made in order to explore the wide architectural design space at the early design phase. In this work, we present a novel manycore simulator that achieves fast and scalable performance with a trace-driven parallel simulation technique. Since the communication delay affects the simulation accuracy heavily, the proposed simulator supports a high-speed accurate on-chip network model, which can capture link/buffer congestions. Its development is motivated by an industry project to design a new manycore architecture with 96 cores with a NoC architecture. Experimental results show that the proposed simulator could run real parallel benchmark applications with more than 450 Kcycles/sec/core. It marks a Pareto-optimal simulator between speed and accuracy, compared with existent simulators. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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