Power reducing techniques for clocked CMOS PLAs

Autor:	R.F. Hobson
Rok vydání:	2002
Předmět:	Integrated injection logic Pass transistor logic CMOS Computer science Logic gate Depletion-load NMOS logic Hardware_INTEGRATEDCIRCUITS Electronic engineering Logic family Simple programmable logic device Programmable logic array Hardware_LOGICDESIGN
Zdroj:	Great Lakes Symposium on VLSI
DOI:	10.1109/glsv.1998.665196
Popis:	Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocked PLA techniques is possible.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::2878185a449ba1482d1d62e9116d9256 https://doi.org/10.1109/glsv.1998.665196 Zobrazit plný text záznamu