Level synthesis approach to application-specific integrated circuits (ASIC) design
| Autor: | O. Levia |
|---|---|
| Rok vydání: | 2003 |
| Předmět: |
Documentation
Application-specific integrated circuit Computer architecture Computer science Process (engineering) Constrained optimization Routing (electronic design automation) Physical design Design methods Engineering design process Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN |
| Zdroj: | Proceedings., Second Annual IEEE ASIC Seminar and Exhibit. |
| DOI: | 10.1109/asic.1989.123164 |
| Popis: | A high-level synthesis approach to ASIC design is presented. The tutorial focuses on the solutions a synthesis system can offer in an environment where ASIC design problems are becoming increasingly complex. In particular, it is shown how a synthesis system can help in shortening the design cycle and documentation of the design process and aid the design verification. The synthesis process is defined as applied to ASIC design. The benefits synthesis can offer an ASIC designer are discussed. The requirements that a synthesis approach places on the design process and the designer are discussed. A simplified design example is presented. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|