A parallel-amplification parallel-summation logarithmic amplifier for UHF RFID reader

Autor:	Zhang Xiao-jun, Lai Zongsheng, Zhang Yong, Chen Lei
Rok vydání:	2009
Předmět:	Log amplifier Engineering CMOS Ultra high frequency Ask price business.industry Dynamic range Bandwidth (signal processing) Electrical engineering Electronic engineering Dissipation business High dynamic range
Zdroj:	2009 IEEE 8th International Conference on ASIC.
DOI:	10.1109/asicon.2009.5351373
Popis:	This paper describes a four gain paths parallel-amplification parallel-summation logarithmic amplifier (PPLA). It is used in the UHF RFID Reader as a part of the ASK demodulating system to compress the high dynamic range input signal. Compared with the successive detection logarithmic amplifier (SDLA), the PPLA has wider bandwidth, and is easier to meet requirement of the system stability. The presented PPLA is implemented in IBM 0.18um CMOS technology with dynamic range of 70dB, bandwidth of 1MHz, and power dissipation of 19 mW1.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::28597acba726de495890fadc9fa348a6 https://doi.org/10.1109/asicon.2009.5351373 Zobrazit plný text záznamu