A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests

Autor:	Shunichi Kaeriyama, Masayuki Mizuno, Mikihiro Kajita
Rok vydání:	2011
Předmět:	Engineering business.industry Clock signal Underclocking Clock rate Electrical engineering Clock gating Digital clock manager Electronic Optical and Magnetic Materials Clock domain crossing Electronic engineering Clock generator Electrical and Electronic Engineering business CPU multiplier
Zdroj:	IEICE Transactions on Electronics. :102-109
ISSN:	1745-1353 0916-8524
DOI:	10.1587/transele.e94.c.102
Popis:	A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65nm CMOS technology. It demonstrates frequency syntheses of 1.68GHz to 3GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5ps to 9.4ps with a 3.125ps step resolution.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::2855fc1d2c4b7561823c44384d2522e0 https://doi.org/10.1587/transele.e94.c.102 Zobrazit plný text záznamu