| Popis: |
This paper discusses pre- and post-silicon electrical validation requirements for highly integrated designs and highlights the need for large-scale modeling and simulation of analog components in the context of validation. Current fast SPICE tools and Analog-Mixed Signal simulation do not provide the speed and scalability necessary to perform full cluster or system-level verification of high-speed IO links or to perform a variability analysis of these circuits. This paper outlines a method to scale the simulation of these circuits with correct accounting of voltage and temperature fluctuations, within-die and die-to-die variations, and platform uncertainty, with little loss in accuracy. The results are illustrated on a self-biased PLL example and illustrate the tremendous speedup that can be achieved while maintaining a comparable accuracy to SPICE for the behaviors that are modeled. |
