| Autor: |
Balaji T.S, Nihitha S.S, Karthik. S, K. Priyadarsini |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
International Journal of Engineering & Technology. 7:1037 |
| ISSN: |
2227-524X |
| DOI: |
10.14419/ijet.v7i4.10.26665 |
| Popis: |
Power optimization has become an essential and major source of concern at the system level design. With the shrink in transistor length and the attractiveness of handy electronic devices, power dissipation has become a serious issue. System level power optimization technique gains more popularity since many techniques can be applied in reduction of power. Although, there are numerous techniques to reduce power dissipation, simpler methods has not been implemented on a system level. In this paper we use profiling technique, a process which helps one to know which portion of the function takes more time compared to other during the simulation. The portion which takes large time for simulation is port mapped to the FPGA while the rest is assigned to the processor. By this technique we can see considerable amount of power savings. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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