25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections
| Autor: | Jiho Joo, Jeongho Hwang, Gyu-Seob Jeong, Kwanseo Park, Gyungock Kim, Dae-Young Yun, Jinhyung Lee, Hong Seok Choi, Kwangho Lee, Han-Gon Ko, Hyungrok Do, Daehyun Koh, Deog-Kyoon Jeong |
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| Rok vydání: | 2018 |
| Předmět: |
Physics
Optical fiber business.industry 020208 electrical & electronic engineering Transmitter SerDes 02 engineering and technology 020202 computer hardware & architecture law.invention Optics CMOS law 0202 electrical engineering electronic engineering information engineering Sensitivity (control systems) Electrical and Electronic Engineering Transceiver S-LINK business Jitter |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 65:1395-1399 |
| ISSN: | 1558-3791 1549-7747 |
| Popis: | This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be −7.5 dBm at 21.2 Gb/s with an optical excitation, and $120~{\mu }\text{A}_{\text{pp}}$ at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b. |
| Databáze: | OpenAIRE |
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