A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms
| Autor: | Zhe-Hui Lin, Hiroyuki Yamauchi, Chih-Sheng Lin, Tzu-Kun Ku, Cha-Hsin Lin, Ming-Pin Chen, Meng-Fan Chang, Shyh-Shyuan Sheu, Wei-Cheng Wu, Yen-Huei Chen |
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| Rok vydání: | 2013 |
| Předmět: |
Engineering
business.industry Interface (computing) Sorting Process (computing) Master/slave Hardware_PERFORMANCEANDRELIABILITY Power (physics) Embedded system Universal memory Scalability Hardware_INTEGRATEDCIRCUITS Electronic engineering Static random-access memory Electrical and Electronic Engineering business |
| Zdroj: | IEEE Journal of Solid-State Circuits. 48:1521-1529 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2013.2253413 |
| Popis: | TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers (NSTACK) in various configurations to form a universal-memory-capacity platform (UMCP). However, conventional 3D memories suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large NSTACK with wide IO, especially using via-last TSVs. This work proposes a semi-master-slave (SMS) memory structure with self-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory devices, while providing high scalability in NSTACK for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various NSTACK; 2) high tolerance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, particularly in UMCP designs with scalable NSTACK and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip confirmed the functionality and demonstrated superior scalability in NSTACK with small speed overheads. |
| Databáze: | OpenAIRE |
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