FunState-an internal design representation for codesign
| Autor: | Dirk Ziegenbein, Rolf Ernst, Matthias Gries, Lothar Thiele, K. Strehl, Jürgen Teich |
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| Rok vydání: | 2001 |
| Předmět: |
Marked graph
Functional programming Signal programming Finite-state machine Theoretical computer science Dataflow Computer science Model of computation Dynamic priority scheduling Petri net Hardware and Architecture Formal specification High-level synthesis Electrical and Electronic Engineering Formal verification Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9:524-544 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/92.931229 |
| Popis: | In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in the form of a periodic graph. The feasibility of the novel approach is shown with an asynchronous transfer mode switch example. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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