Printed-circuit board (PCB) charge induced product yield-loss during the final test

Autor:	Manjunatha Prabhu, Jian-Hsing Lee, Mahadeva Iyer Natarajan, Kunihiko Takahashi
Rok vydání:	2015
Předmět:	Production line Engineering business.industry Electrical engineering Volt Chip law.invention Capacitor Printed circuit board law Logic gate Resistor business Voltage
Zdroj:	IRPS
DOI:	10.1109/irps.2015.7112823
Popis:	The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that the voltage is high enough to damage the components of the low voltage circuits (1.8V), but is still too low to turn on the ESD protection device.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::27b6f5e127dde884bd8ee5646fb82eac https://doi.org/10.1109/irps.2015.7112823 Zobrazit plný text záznamu